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ETROC2 Test Card Specifications

  • Authors: Andrew Peck, Daniel Spitzbart, Panos Gkountoumis, Ryan Heller, Chris Madrid, Sergey Los

  • Modification Date: 2023-01-10 12:03

Table of Contents

  1. ETROC2 Test Card Specifications
    1. Resources
    2. Specifications
  2. Design Notes
    1. LGAD Preamp
    2. ETROC1 Mounting

Resources

Specifications

The ETROC2 test card is a “module PCB” optimized for use in the test beam environment. This involves electrical and mechanical changes which make it easier to operate on the bench and in the test beam, and mean that it deviates somewhat from the “CMS-like” module PCB.

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The test card shall have:

  1. A single ETROC, with the option to either bump-bond the ETROC or to wire-bond the ETROC to an adjacent 2x2 LGAD
    • In both cases, the PCB must provide wire bond landing pads for bonding the bias voltage to the LGAD.
    • In the wire-bonded case, the PCB must provide drilled holes through the PCB for β-testing.
    • In the wire-bonded case, the PCB must also provide the ability to wire bond the LGAD guard ring to the ETROC2 ground pads. c.f. the ETROC bond diagram (this means that the position of the LGAD should be on the side of the ETROC close to the pads?)
    • The ETROC should be as close to the edge of the PCB as possible
  2. The option for a discrete amplifier, which can be wirebonded to a small LGAD for standalone testing
    • A right angle SMA connector will connect between the PCB and the amplified signal
  3. Options for powering the ETROC. The power source should be selectable with e.g. 2.54mm headers and a jumper.
  4. Test points to allow probing if necessary:
    • Test points for downlink clock, downlink data
    • Test points for the I2C bus
    • Test points for the 1.2V ETROC power
  5. A flat backside (no back side components, no through hole components) to facilitate mounting on a PCB
  6. A connector for LGAD bias (0 to -550V).
    • SMA or BNC?
    • An RC bias voltage filtering scheme will be adopted from the ETROC1 test card
  7. Thermistors near LGAD with a connection to the readout board analog inputs
    • Part number:

Design Notes

LGAD Preamp

  • SiPM Preamp Schematics
  • Preamp needs input and output decoupling capacitors (0.1uf),
  • L1 and C2 are not needed
  • R4 is 1kOhm and provides dc biasing of an LGAD pixel
  • Input and output traces are 50 ohm
  • One more thing - the 130 ohm R1 is optimized for +6V power supply.
    • If you decide to use a different voltage - check the data sheet for recommended values.

ETROC1 Mounting

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The size is 4x4mm minimum, there are 4 holes in the center, in a 1.4 x 1.4 mm square pattern, non-plated, 1mm diameter.

The pad itself is at -BV and bypassed with five 47pf caps to a GND pad on the next layer (I’m sure you’ll have more than 2 layers). In my case that GND was connected to a mounting pad under the ETROC chip, but it turned out the ETROC substrate is not a good ground. So, it’s better if that GND pad on layer2 (sized more or less to the ’-BV’ pad) is connected to several wire-bonding pads between the ETROC2 and LGAD, those pads will be wire-bonded to the GND pads on ETROC (designed for bump-bonded LGAD’s guard ring). That way the LGAD’s BV will be referenced to those guard ring GND pads. Maybe those GND wire-bonding pads can be arranged not between the ETROC and LGAD, but at the adjacent sides of the ETROC, since the ETROC GND pads are all around the perimeter of the chip (you can see those around the 5x5 pixel pad structure in slide6 of attached wire-bonding diagram).