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System

Overview

The ETL system test setup consists of the following main components:

  • Backend board (KCU 105): Communicates with the frontend (readout board, ETROC) through optical high speed links (2 uplinks RB->KCU, 1 downlink KCU->RB). Controlled from a PC through local network using IPBus library within the tamalero software package. Provides the LHC clock to the frontend and ETROC.

  • Front End Readout Board: Up- and downlink run through the VTRX+ optical transceiver. Two lpGBTs are used on all readout boards, one in transceiver mode (called either main or DAQ lpGBT) and one in transmitter mode (called secondary or TRIGGER lpGBT). Depending on the version of the readout board version either a GBT-SCA chip or a MUX64 chip is used to extend monitoring capabilites.

  • Module: Contains up to 4 ETROC chips bump bonded to 16x16 pixel LGAD sensors. The ETROC chip reads out the analog signal from each pixel, amplifies it and digitizes the signal in a low power TDC. Data from the ETROC is sent out through one or two elinks with a programmable data rate between 320 and 1280 Mbps. The ETROC chips are configured through I2C, where the I2C controller can be either one of the lpGBTs or GBT-SCA (RB version dependent).