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Readout Board Specifications

Table of Contents

  1. Readout Board Specifications
    1. Description
    2. Quantities
    3. Interfaces
      1. Power Board Interface
      2. Module Interface
      3. Fiber Optic Interface
      4. Low Voltage Interface
      5. Programming Interface
    4. Signal Connectivity
      1. I2C
      2. IO
      3. Uplinks
      4. Downlinks
      5. Clocking
      6. VTRX
    5. Monitoring
    6. Low Voltage Distribution
    7. Bias Voltage Distribution
    8. Mechanics
      1. Outer Dimensions
      2. Screw Holes & Sizes
      3. Thickness
      4. Drawings
      5. Module Mechanics
    9. History

Description

The Readout Board will be designed in 3 different flavors, called the RB-3, RB-6, and RB-7, where the suffix number represents the number of “full-modules” that the Readout Board services.

  • An RB-3 will interface with 3 modules, meaning 12 ETROCs and 12 sensors.
  • An RB-6 will interface with 6 modules, meaning 24 ETROCs and 24 sensors.
  • An RB-7 will interface with 7 modules, meaning 28 ETROCs and 28 sensors.

The Readout Board consists of one or more lpGBTs, one or more GBT-SCA, a VTRX+, a number of linPOL12 regulators, and associated connectors / passive components required to interface with the external systems.

  • Each RB will have 1 GBT-SCA
  • Each RB will have 2 or 3 lpGBTs
    • All RBs will have 2 lpGBTs used for DAQ which are connected to the VTRX+
    • The RB7 will have an additional lpGBT used for monitoring only
  • Each RB will have 1 VTRX+
  • Each RB will have 6 linPOL12s
    • 2 for VTRX+ RX
    • 2 for VTRX+ TX
    • 1 for GBT-SCA analog power
    • 1 for GBT-SCA digital power

Quantities

  • The number of the different flavors of RB in ETL is:
    • RB-3: UNKNOWN
    • RB-6: UNKNOWN
    • RB-7: UNKNOWN
  • The quantity to fabricate, including spares, will be:
    • RB-3: UNKNOWN
    • RB-6: UNKNOWN
    • RB-7: UNKNOWN

Interfaces

Power Board Interface

The interface to the power board will consist of:

Module Interface

  1. Signal Interface

    The signal interface to the module will consist of:

    • The module will use connector part number UNKNOWN.
    • The pinout of the module connectors is UNKNOWN.
    • The placement of these connectors is UNKNOWN.

  2. BV Interface

    The BV interface to the module will consist of:

    • The BV to module interface will use connector part number UNKNOWN.
    • The pinout of these connectors is UNKNOWN.
    • The placement of these connectors is UNKNOWN.

Fiber Optic Interface

The fiber optic interface to CMS is through a VTRX+. The Readout Board will host both the VTRX+, as well as the MT Ferrule that is required to connect between the VTRX+ and a fanout.

  • The size of the cutout for the MT ferrule is UNKNOWN.
  • The location of the cutout for the MT ferrule is:
    • RB-3: UNKNOWN.
    • RB-6: UNKNOWN.
    • RB-7: UNKNOWN.

Low Voltage Interface

The Readout Board will connect to the low voltage supply to receive ~8V power.

  • The part number for the LV connector is UNKNOWN.
  • The pinout for the LV connector is UNKNOWN.
  • The placement for the LV connector is UNKNOWN.

Programming Interface

  • The Readout Board will NOT provide a programming interface to allow fusing/configuration of the lpGBT through I2C.

Signal Connectivity

I2C

  • The GBT-SCA will provide one I2C connection for each module.
  • All ETROCs in a module will share an I2C master.
  • The Readout Board will provide strong I2C pull-ups.
    • It is assumed that the modules will not, and have only weak pull-ups.

IO

  • A GBT-SCA provides 32 tri-stateable 1.5V GPIO
  • An LPGBT provides 16 tri-stateable 1.2V GPIO
  • These IO will be allocated as:
Table 1: Allocation of GPIO on the Readout Board
  Source RB-3 RB-6 RB-7
GBT-SCA RESETB lpGBT 1 1 1
VTRX LD_RESETB lpGBT 1 1 1
VTRX LD_DIS lpGBT 1 1 1
Module Reset GBT-SCA 3 6 7
WS Reset GBT-SCA 3 6 7
PB Good GBT-SCA 4 8 10
PB Enable GBT-SCA 4 8 10
Available   64 64 64
Total   17 31 37
  • The module reset signals will be pulled up to the 1.2V lpGBT supply by the readout board
  • The Power Good signals will be pulled up to the 1.2V lpGBT supply by the readout board
    • They are assumed to be open-collector or open-drain signals without pullups on the DC/DC converters.
  • The Power Enable signals will be pulled down to ground by the readout board.
    • They will be driven to 1.5V to enable the DC/DC converters. This is assumed to be sufficient to turn on the BPOL modules.

Uplinks carry data from the front-end to the back-end.

  • These uplinks will not be phase length matched.

  • Quantity

    • RB-3 will have 24 uplinks
    • RB-6 will have 48 uplinks
    • RB-7 will have 56 uplinks

  • Data Rates

    • RB-3 will operate at up to 640 Mbps
    • RB-6 will operate at up to 320 Mbps
    • RB-7 will operate at up to 320 Mbps

Downlinks carry data from the back-end to the front-end.

  • The Readout Board will deliver to each module two downlinks that provide a “fast command” interface to the ETROC.
  • These fast-command downlinks will run at 320 Mbps.
  • The fast command downlinks will be multi-dropped on the module, with each downlink serving 2 ETROCs.
    • 6 downlinks for the RB-3, 12 downlinks for the RB-6, and 14 downlinks for the RB-7.
  • These downlinks will not be phase length matched between modules, but will be phase length matched within modules and to their respective clocks.

Clocking

  • The Readout Board will be responsible for delivering a 40 MHz point-to-point clock to each of the ETROCs it connects to.
    • 12 clocks for the RB-3, 24 clocks for the RB-6, and 28 clocks for the RB-7.
  • These clocks will not be phase length matched between modules, but will be phase length matched within modules.
  • The clock will be distributed only from the master lpGBT; the slave lpGBT clock outputs will not be used due to radiation intolerance.

VTRX

Monitoring

A GBT-SCA ASIC provides 31 analog inputs with 12-bit resolution, and 4 analog outputs with 8-bit resolution, with a range of 0 to 1V.

An lpGBT provides 8 analog inputs with 10-bit resolution and 1 analog output with 12-bit resolution.

An GBT-SCA ASIC requires an 80 Mbps e-link for operation. The GBT-SCA does not support multi-drop operation 1, so each SCA requires an individual elink. On the longest RB-7, all of the elink groups are used by the ETROCs themselves. This limits the number of SCAs on an RB-7 to one.

The number of monitoring channels available is planned to be:

  • RB3 and RB6: 47 channels
    • 16 10 bit channels (2x lpgbt), and 31 12 bit channels (1x SCA)
  • RB7: 55 channels
    • 24 10 bit channels (3x lpgbt), and 31 12 bit channels (1x SCA)

The Readout Board will monitor the following analog channels:

Table 2: Allocation of monitoring signals on the Readout Board
Sensor Type Monitored By Divider LSB Range Qty. RB-3 Qty. RB-6 Qty. RB-7
Sensor BV Voltage GBT-SCA 82/100082 2.980e-01 V 1220.3 V 3 6 7
PB +1.2V Voltage GBT-SCA 2.0/4.2 5.128e-04 V 2.1 V 4 8 10
RB LV Voltage lpGBT 1/11 1.075e-02 V 11.0 V 1 1 1
VTRX +2.5V RX Voltage lpGBT 1.5/4.5 2.933e-03 V 3.0 V 1 1 1
VTRX +2.5V TX Voltage lpGBT 1.5/4.5 2.933e-03 V 3.0 V 1 1 1
GBTX +1.5VD Voltage lpGBT 2/3.5 1.711e-03 V 1.8 V 1 1 1
GBTX +1.5VA Voltage lpGBT 2/3.5 1.711e-03 V 1.8 V 1 1 1
VTRX RSSI Photocurrent lpGBT       1 1 1
VTRX TEMP Temperature lpGBT       1 1 1
RB TEMP Temperature lpGBT 1     1 1 1
ETROC AMUX Voltage GBT-SCA 1 2.442e-04 V 1.0 V 12 24 28
Available           47 47 55
Totals           27 46 53
  • The power board does NOT have temperature sensors aside from those connected to DSS.
  • All voltage dividers will be formed of 0.5% tolerance resistors.
  • All analog inputs will be decoupled by 0.1 uF capacitors.
  • FIXME: Voltage dividers should be revisited

Low Voltage Distribution

  • The Readout Board will provide four 47 uF capacitors connected to each 1.2V ETROC supply.
    • There will be no additional filtering such as inductors.
  • Analog and digital power for the ETROC will not be distinguished.
  • The low voltage will be ganged such that UNKNOWN (2 or 3, depending on 2A or 3A scenario) ETROCs share a common power supply.

Bias Voltage Distribution

  • Bias voltage will be a maximum of 550 volts 2.
  • The readout board will support of maximum bias voltage granularity of 1 channel per module, with the capability to gang together multiple modules.
  • The Readout Board will provide a filter for each bias voltage channel consisting of a 200 ohm resistor and 1500 pF capacitor, which will be rated for at least 1000V.
  • Bias voltage interlock safety will be provided through an UNKNOWN mechanism.

Mechanics

Outer Dimensions

  • The outer dimension of the Readout Board will follow an UNKNOWN shape

Screw Holes & Sizes

  • The Readout Board will have UNKNOWN mounting holes of size UNKNOWN in the following locations:
    1. UNKNOWN

Thickness

  • The Readout Board will be 1.0mm thick with a manufacturing specification of ± 10%.

Drawings

A drawing of the Readout Board is available at UNKNOWN.

Module Mechanics

  • the module shall be aligned to the Readout Board using an UNKNOWN keying mechanism

History

test

Date Author Change
2022/03/14 AP Initial
2022/08/26 AP Update analog monitoring table; remove programming interface; update uplink cnt
2022/09/12 AP Add note about interlock (lack of?)
2022/09/15 AP Require ETROC analog mux; 1 SCA / RB, 3 lpGBTs on RB7
2022/09/15 AP Add RB quantity fields

Footnotes

1 https://lpgbt-support.web.cern.ch/t/multidrop-ec/529/1

2 https://indico.cern.ch/event/1131302/contributions/4749462/attachments/2398248/4100919/heller_LGAD_survival_trento_march2022.pdf