Module Specifications

Authors: Andrew Peck, Daniel Spitzbart
Modification Date: 2022-08-26 14:10
Status: This document is missing 25 pieces of information concerning 43 specifications
- Specifications are 41.9% complete.
A pdf version of this document can be found here. Please check the timestamp to ensure it is up to date. The master copy of this document is an emacs org mode file found here.

Specifications

Description

The module PCB is a simple printed circuit board which will host two LGAD sensors, and two LGAD modules. To support these, it will have wire bond pads, a variety of passive components (capacitors and resistors), and a connector interface to attach to a Readout Board (RB).

Documentation for the ETROC does not exist.

Layout

We denote the “top” side of the PCB as that containing the sensor.
- On the top, the 4 ETROCs rest on four square pads in positions 1, 2, 3, and 4, which are respectively near the HV1, HV2, HV3, and HV4 markings. The edge corner cutout on the module PCB is by 3 and HV3.
We denote the “bottom” side of the PCB as that containing the module and BV connectors.

Sensor Placement

The dimensions of a Sensor+ETROC assembly is UNKNOWN × UNKNOWN mm.
The position of the two Sensor+ETROC assemblies are (positions relative to UNKNOWN):
- x= UNKNOWN mm; y= UNKNOWN mm.
- x= UNKNOWN mm; y= UNKNOWN mm.

Wire bonding

A wire bonding diagram of an ETROC is shown in ¹ and ².
The ETROC pinout is shown in ³.
The pad pitch will be UNKNOWN mm.
The pad aperture will be UNKNOWN × UNKNOWN mm.
The pad aperture will be NSMD (non-solder-mask-defined) with the mask oversized by UNKNOWN mm.
The wire bond pads will be located UNKNOWN mm from the edge of the ETROC (measured edge-to-edge).

Grounding

The RB will geometrically isolate analog and digital ground, with specified areas of the PCB filled by a digital ground pour, and others filled by an analog ground pour. The digital and analog grounds will be connected together at a single point. Alternatively, the grounds may be separated into ASIC domain vs. HV domain
- A drawing of proposed grounding schemes are shown in ⁴.
- Final grounding scheme is yet UNKNOWN
The entire plane under the ETROC shall be grounded according to the aforementioned grounding scheme, with no break in the grounding for vias.
The exposed ground surface shall be exposed gold (ENIG) with no solder mask for maximum flatness.

Fiducial Markings

The module PCB will have on its top side 4 fiducial markers, composed of circles with crosses through them. These markers shall be placed with their centers 2.0 mm from the corners of the board. The markers should be clear of solder mask.

Connectivity

Readout Board Interface

Signal Interface

The signal interface to the readout board will consist of:
- The readout board will use connector part number UNKNOWN.
- The pinout of the readout board connectors is UNKNOWN.
- The placement of these connectors is UNKNOWN.
BV Interface

The BV interface to the readout board will consist of 8 spring connectors (4 BV pads, and 4 BV return pads)
- The BV to readout board interface will use connector part number TE 1551631-5, a spring connector with minimum working height of 0.6mm and maximum current of 0.5A.
  - Product page: https://www.te.com/usa-en/product-1551631-5.html
- The spring connectors will be hosted on the RB, so the module need only to expose gold pads in the correct locations.
- The placement of these connectors is UNKNOWN.

I2C

The module carries I2C signals (SCL, SCK) from the readout board and distributes it to the 4 ETROCs in a star topology.
The module PCB will provide independent I2C addresses for each ETROC on a module. Addresses will be 0/1/2/3 corresponding to the slot, and are set directly by wire bonds.
- Addresses will not be set by resistors, and can not be modified.
- The ETROC2 address pins have internal 40k pull-down resistors ⁵.
- For ETROC2 waveform sampler, the I2C pins do not have integrated pull-ups/downs.
The module PCB will not provide pull-up resistors on I2C lines. These will be provided by the host-system.
A slot address will be set by the readout board, so I2C address bits ’(2 3 4) will be connected from the module to the readout board.

Low Voltage

The module must receive +1.2V from the readout board, and distribute it to the ETROCs in a low inductance, low resistance path.

Each module will receive two possibly independent +1.2V supplies.
- They will not be connected together in any way on the module, but may be ganged together on the RB.
Decoupling
- The module will provide decoupling capacitors on the +1.2V supplies. The power filtering network will be composed of:
  1. UNKNOWN resistors of UNKNOWN values
- Decoupling capacitors will be placed as close as possible to the ETROC, and follow standard practices to maintain low inductance connections.
- Decoupling capacitors will be suitably rated to minimize DC bias effects.
- To reduce temperature dependence, ceramics will be chosen where possible with minimal temperature dependence (e.g. X7R).

Signal Connectivity

Each module will receive two 320 MHz downlinks from the RB
Each module will receive four 40 MHz clocks from the RB
- The clocks shall be length matched and skewed such that for a multi-drop pair of lpGBTs, the clock and data are synchronized at each ETROC’s input pads.
Each module will have 8 uplinks (2 per ETROC) operating at up to 640 Mbps.
The module will connect per 1 temperature sensor and 1 VREF monitor per ETROC (8 analog signals total)

The module will connect per 1 reset and 1 waveform sampler reset for each module

Signal	Count	Direction	Description
1V2 [3:0]	4	IN	Power for ETROCS 0 to 3
Elinks [7:0]	8	OUT	Up to 640 Mbps Elinks
Clock [3:0]	4	IN
VREF [3:0]	4	OUT
TEMP [3:0]	4	OUT
ADDR [4:2]	3	IN
RESET	1	IN
WS RESET	1	IN
BV [3:0]	4	IN
BV Return [3:0]	4	OUT
GND	1

Bias Voltage

The module will receive bias voltage from the readout board and distribute it to the modules.
- BV will be a maximum of negative 550 volts ⁶.
- The module will support 4 independent BV interfaces, to reduce to routing burden as well as to allow flexibility for module powering.
- Decoupling
  - The BV may or may not be decoupled/filtered on the module PCB UNKNOWN

Mechanics

Outer Dimensions

The outer dimension of the Module PCB will follow a rectangular shape, with dimensions of UNKNOWN × UNKNOWN.

Screw Holes & Sizes

The Module PCB will have 2 mounting holes of diameter 2.2 mm, centered along the vertical axis of the board, offset from the edge by 1.650 mm.

Standoff / mounting mechanics

The module PCB will have a surface mount standoff to allow affixing it securely to the readout board. It will be place in UNKNOWN.

Thickness

The Module PCB will be 0.5mm thick with a manufacturing specification of ± 10%.

Drawings

A drawing of the Module PCB is available at UNKNOWN.
A drawing of the ETROC and sensor is available at ⁴.

Mechanical Interface

the module shall be aligned to the Readout Board using an UNKNOWN keying mechanism

History

Date	Author	Change
2022/03/14	AP	Initial
2022/05/19	AP	Specify bias voltage and downlink data rate
2022/05/31	AP	Add final-not-final ETROC pinout/bonding
2022/05/31	AP	Add ETROC grounding / mechanical diagram
2022/06/09	AP	Updates to module signal assignments
2022/08/26	AP	Fix uplink counting