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Test beam requirements

Data Rates

Per these slides:

https://indico.cern.ch/event/1209882/contributions/5088089/attachments/2525450/4343480/preparing_for_beam_test_oct10.pdf

  • Event rates \~10k events in 4s bursts (56 seconds of silence). Need to either:
    • buffer events in FPGA memory; send to PC after one “run”;
    • OR: careful streaming of data to PC continuously.
// parameters
double occupancy = 0.1;
float time = 4;
int events = 10000;
int word_size = 64;

// calculations
float mean_packet_size = 64*2 + 64*occupancy*256;
float dump_size = events * mean_packet_size;
float data_rate = dump_size / time;

printf("@ %3.1f%% Occupancy: dump size = %f Mb / %2.1f s = %f Mbps", occupancy*100, dump_size/1E6, time, data_rate/1E6);

@ 10.0% Occupancy: dump size = 17.664000 Mb / 4.0 s = 4.416000 Mbps

Clock Synchronization

Clock signal also must be distributed to oscilloscope time reference.

External Trigger

An NIM -> CMOS / LVDS converter board is being developed to connect the NIM trigger to the KCU105. The KCU105 has an 8x oversampling trigger input, requiring a minimum pulse width of 3.125 ns to receive the external trigger.

Module Requirements

Initial testing: build simple module PCB “v2”

  • Allow operation with 1-2 ETROC2 and 1 LGAD
  • Compatible with beta testing (sensor offset from RB)
  • Transition to bump-bonded system later, eventually 4x ETROC2 on realistic module
  • Need all sensor/chips to be independent (e.g switches) bad chip/sensor can’t kill module

Mechanics

  • Cold box